IEEE 1450.6.1-2009 pdf download

IEEE 1450.6.1-2009 pdf download.IEEE Standard for Describing On-Chip Scan Compression
1.3 Conceptual data flow Figure 1 shows the OCI conceptual data flow from test logic insertion to pattern generation and from pattern generation to diagnosis. Both the OCI flow (assuming a different vendor for each stage) and the current flow (same vendor for each stage) are shown. Since same-vendor tools have their own way of linking different stages of the flow together, OCI is only needed for changing stages when any previous step was completed by a different vendor. If different vendors were used, then all the data OCI would normally add in the previous stages is needed.
Figure 1—Conceptual OCI flow The test logic insertion stage has the best understanding of the test structure being implemented. Test logic insertion tools are developed based on specific compression structures and have many special design rule checks implemented so customers have as good a chance as possible to generate working, highly effective patterns the first time.
The time and knowledge necessary to develop all of the design rule checks is significant. Due to this, the OCI flow presumes the pattern generation tool does not need to perform test structure verification. In the case where a design house is integrating a core with in-house design logic, the test structure in the core is presumed to be verified by the core provider and all core-level OCI information needed for pattern generation shall be in the OCI-compliant CTL file the core provider gives the design house.
The design house integrating the core is responsible for generating and verifying the final OCI information passed to pattern generation. The OCI-specific information passed from test logic insertion to pattern generation includes pattern sequence restrictions, a description of compression hardware, netlist mapping points, and vendor-specific data to ensure vendor flows are as easy to use as possible when using OCI. For a more detailed description of how CTL is leveraged to pass information from test logic insertion to pattern generation, see 1.4.
The pattern generation stage can be very time consuming. The automatic test pattern generator (ATPG) determines which logic values are needed on scan cells to detect the most faults by each test pattern. After a pattern is generated, it is then simulated to determine how many faulty locations have been detected. This sequence is repeated until as many as possible faulty locations have been detected. For chips without on- chip scan compression, the value loaded and unloaded from each scan cell can be mapped directly to a unique value loaded into the chip and to a unique value unloaded from the chip. Only sequence definitions that describe how to initialize, load, unload, and apply tests are needed by pattern generation for this case.
On-chip scan compression needs more information. Putting a logic value in a scan cell requires a value to be loaded into the chip at a previous point in time and likely forces other scan cells to be put to certain logic values. Checking that a value is in a scan cell may require values in masking logic or on other scan cells. Also, on-chip scan compression hardware may restrict the length of a sequence or require a relationship between sequences because of how the hardware is implemented. To do pattern generation efficiently, OCI passes pattern generation sequences, sequence limitations/relationships, and symbolic descriptions of the compression hardware created by the test logic insertion stage.
The output test patterns generated by pattern generation need to be diagnosable using both EDA diagnosis, that can isolate to a gate or net, and on the tester, where isolation is possible due to the failing scan cell or scan chain. To enable this capability, the pattern generation stage shall identify key events in the pattern data and pass this information to diagnosis. The information is passed through OCI by updating the sequences and/or by adding information to the test pattern data. For a more detailed description of how CTL is leveraged to pass information from pattern generation to diagnosis, see 1.4.IEEE 1450.6.1 pdf download.IEEE 1450.6.1-2009 pdf download